1. Technical field
The present invention relates to network handling systems and more particularly to a method and a system for asynchronously serializing or deserializing data.
2. Description of prior art
There are many network handling systems in the prior art which transmit data between a processor system and a peripheral device across a serial data transmission link. Generally these network handling systems use network device interfacing the processor bus and the serial link in which various adaptations are performed like parallel to series data conversion with clocks resynchronization mechanism. Among those systems are the following patents which disclose some network devices.
U.S. Pat. No. 5,422,914 from Snyder, discloses a data synchronization system for synchronizing data communication between two devices operating at different clock frequencies, the first frequency being greater than the second frequency in an integer ratio. The system has control circuitry, first circuitry and second circuitry for generating several fractional portions of the slowest clock period, these portions representing a corresponding state of a finite state machine. This system operates with a ratio of the clock frequencies which may be expressed as N/M in simplest form where N and M are integers.
In other known systems, the frequency of the receiver device is not as in the previous cited patent necessarily synchronized to the frequency of the emitter device to transfer the data. For example U.S. Pat. No. 4,907,186 from Racey discloses an electronic interface circuit for receiving high speed serial data and converting to parallel data, by providing an input interface, a serial to parallel data converter a FIFO buffer memory and an output interface. A control circuit receives a synchronous clock signal from the data source and derives therefrom a plurality of clocking signals to clock the serial data. Whereas in this system the emitter and the receiver clocks are independent for transferring the data, the operating range of these clocks is limited by the control circuit which generates the derived serial clocks.
The circuits of these references are not acceptable for present day advanced networking applications, wherein the serial frequency may vary in a wide operating range comprising the parallel frequency. Moreover, none of the known systems offers an efficient solution to network handling systems wherein the parallel and the serial frequencies are asynchronous while these values are either equal or in close range.
In this configuration different drawbacks may arise. A first one is the well-known metastability problem which may occur on the resynchronization circuit because the serial clock may be sampled to the parallel clock on an edge transition of the serial clock, and therefore the set-up and hold times may be violated. A second problem occurs when the parallel/serial ratio between the two clocks are in the close range of the unit. In that case, sampling edges may be lost which results in lost data.
Accordingly, it would be desirable to be able to provide a new network device to avoid the aforementioned problems.